1. Field of the Invention
The present invention relates to systems and methods for indicating the status of an ALU operation and, more particularly, to systems and methods for indicating the status of an ALU mathematical operation, pursuant to which the result is based on one or more prior results.
2. Description of Prior Art
Processors, including microprocessors, digital signal processors and microcontrollers, operate by running software programs that are embodied in one or more series of instructions stored in a memory. The processors run the software by fetching the instructions from the series of instructions, decoding the instructions and executing them. A 16-bit arithmetic logic unit (ALU) of a processor, including digital signal processors, are conventionally adept at processing ALU mathematical operation instructions, such as addition operation instructions, that operate on a data word or data byte, and indicates the various statuses affected by the execution of each ALU mathematical operation instruction with status flags. For example, a 16-bit ALU of a processor is adept at performing an addition operation according to an addition mathematical operation instruction on operands represented as a data word and indicating if the result of the addition operation produced an arithmetic result of zero by setting a zero status bit. In general, the statuses affected by a 16-bit ALU mathematical operation is set based on each single 16-bit result produced by the ALU mathematical operation. Accordingly, the statuses affected by a 16-bit ALU mathematical operation may be misleading in conditions where the result is based on one or more prior results and produced by executing a series of ALU mathematical operation instructions. These type of ALU mathematical operations execute in two processing cycles and produce a 16-bit results in each of the processing cycles to form the final result. As a result, the status flags may only indicate the statuses affected by the ALU mathematical operation based on a result produced during the most recent processing cycle instead of the results produced during both processing cycles.
There is a need for a new method of indicating the statuses affected by the performance of an ALU mathematical operation. There is a further need for a new method of indicating the statuses affected by the performance of an ALU mathematical operation producing a final result formed by two distinct semi-results. There is a further need for a new method of indicating the statuses affected by the performance of an ALU mathematical operation for each result produced during the performance of the ALU mathematical operation based on preceding results.